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MAX19505–MAX19507/
MAX19515–MAX19517 Evaluation Kits
Output Timing Control
The Output Timing Control group box contains con-
trols to make adjustments to data and DCLK timing.
The Data Timing Adjust drop-down list adjusts DATA
timing by the selected value. The DCLK Timing Adjust
drop-down list adjusts DCLK timing by the selected
value. By checking the Delay DATA/DCLK by T/2
checkbox, DATA and DCLK outputs are delayed by a
factor of T/2. The Data Aligner Bypass checkbox
bypasses the data aligner delay line when checked.
For more details on output timing control, refer to the
respective IC data sheet.
Clock Controls
The Clock Controls group box contains controls for
manipulating the clock. The Divider drop-down list sets
the clock divider. The Sync Mode drop-down list sets
clock synchronization to either slip or edge mode. In
slip mode, the divided output is forced to skip a state
transition on the third rising edge of the input clock
(CLK) after the rising edge of SYNC. In edge mode, the
divided output is forced to state 0 on the third rising
edge of CLK. The 100 Ohm Input Term. checkbox
switches 100 ? across differential clock inputs when
checked. For more details on clock synchronization
and control, refer to the respective IC data sheet.
Power Management Tab
Power Management Controls
The Power Management group box contains two sets
of controls. The first set is used only when the SHDN
pin on the EV kit is set low; the second set is used only
when the SHDN pin on the EV kit is set high. When
checked, the CHA Active and CHB Active checkbox-
es activate channel A and channel B, respectively, and
power down/standby channel A and channel B when
unchecked. The Standby checkbox toggles between
standby mode when checked and full power-down
mode when unchecked, as long as CHA Active or
CHB Active checkboxes are unchecked. The A+B
Adder mode checkbox toggles between A+B adder
mode when checked and normal dual mode when
unchecked. For more details on power management,
refer to the respective IC data sheet.
Output Driver Power Management Controls
The Output Driver Power Mgmt. Controls group box
contains controls to disable the digital clock (DCLK)
and out-of-range indicator (DOR). The Disable DCLK
checkbox disables the DCLK when checked and the
Disable DOR checkbox disables DOR. Note: Disable
DCLK and disable DOR applies to CMOS modes only.
The Power Down Output State drop-down list sets the
digital output high, low, or to tri-state during power-
down. For more details on output driver power manage-
ment control, refer to the respective IC data sheet.
Simple SPI/SMBus Commands
There are two methods for communicating with the
MAX19505–MAX19507/MAX19515–MAX19517: through
the normal user-interface windows (Figures 1 and 2) or
through the SMBus commands available by selecting
the Interface (Advanced Users) menu item from the
Options menu bar. The Maxim Command Module
Interface window pops up and includes a 3-wire inter-
face tab that allows data to be written to each individ-
ual register.
The SMBus dialog boxes accept numeric data in bina-
ry, decimal, or hexadecimal. Hexadecimal numbers
should be prefixed by $ or 0x. Binary numbers must be
exactly eight digits. See Figure 3 for an illustration of
this tool.
8
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